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Ordering number : ENN7936
LC863548B, LC863540B LC863532B, LC863528B LC863524B, LC863520B LC863516B
Overview
CMOS IC FROM 48K/40K/32K/28K/24K/20K/16K-byte, RAM 640/512-byte on-chip and 176 x 9-bit OSD RAM
8-bit 1-chip Microcontroller
The LC863548/40/32/28/24/20/16B are 8-bit single chip microcontrollers with the following on-chip functional blocks : * CPU : Operable at a minimum bus cycle time of 0.424s * On-chip ROM capacity Program ROM : 48K/40K/32K/28K/24K/20K/16K-bytes CGROM : 16K-bytes * On-chip RAM capacity : 640/512-bytes * OSD RAM : 176 x 9-bits * On-screen display controller * Four channels x 6-bit AD Converter * Three channels x 7-bit PWM * Two channels x 16-bit timer/counter, 14-bit base timer * IIC-bus compliant serial interface circuit (Multi-master type) * ROM correction function * 13-source 8-vectored interrupt system * Integrated system clock generator and display clock generator Only one X'tal oscillator (32.768kHz) for PLL reference is used for both generators. All of the above functions are fabricated on a single chip.
Ver.0.92 62102
73004 JO IM No.7936-1/17
LC863548B/40B/32B/28B/24B/20B/16B
Features
Read-Only Memory (ROM) : 49152 x 8-bits/40960 x 8-bits/32768 x 8-bits/ 28672 x 8-bits/24576 x 8-bits/20480 x 8-bits/ 16384 x 8-bits for program 16128 x 8-bits for CGROM
Random Access Memory (RAM) : 512 x 8-bits (working area) : LC863548B/40B 384 x 8-bits (working area) : LC863532B/28B/24B/20B/16B 128 x 8-bits (working or ROM correction function) 176 x 9-bits (for CRT display) OSD functions * Screen display : 36 characters x 8 lines (by software) * RAM : 176 words (9-bits per word) Display area : 36 words x 4 lines Control area : 8 words x 4 lines * Characters Up to 252 kinds of 16 x 32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16 x 16 dot character font x 2) * Various character attributes Character colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Character background colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Fringe/shadow colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Full screen colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Rounding Underline Italic character (slanting) * Attribute can be changed without spacing * Vertical display start line number can be set for each row independently (Rows can be overlapped) * Horizontal display start position can be set for each row independently * Horizontal pitch (bit 9 to 16) *1 and vertical pitch (bit 1 to 32) can be set for each row independently * Different display modes can be set for each row independently Caption * Text mode/OSD mode 1/OSD mode 2 (Quarter size) /Simplified graphic mode * Ten character sizes *1 Horez. x Vert. = (1 x 1), (1 x 2), (2 x 2), (2 x 4), (0.5 x 0.5) (1.5 x 1), (1.5 x 2), (3 x 2), (3 x 4), (0.75 x 0.5) * Shuttering and scrolling on each row * Simplified Graphic Display *1 Note : range depends on display mode : refer to the manual for details. Bus Cycle Time/Instruction-Cycle Time
Bus cycle time 0.424s 7.5s 91.55s 183.1s Instruction cycle time 0.848s 15.0s 183.1s 366.2s Clock divider 1/2 1/2 1/1 1/2 System clock oscillation Internal VCO (Ref : X'tal 32.768kHz) Internal RC Crystal Crystal Oscillation frequency 14.156MHz 800kHz 32.768kHz 32.768kHz Voltage 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V
Ports * Input/Output Ports : 4 ports (24 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 3 ports (16 terminals) AD converter * 4-channels x 6-bit AD converters
No.7936-2/17
LC863548B/40B/32B/28B/24B/20B/16B
Serial interfaces * IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. PWM output * 3-channels x 7-bit PWM Timer * Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. * Timer 1 : 16-bit timer/ PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : A variable-bit PWM (9 to 16 bits) In mode 0/1, the resolution of timer/PWM is 1 tCYC In mode 2/3, the resolution of timer/PWM is selectable by program ; tCYC or 1/2 tCYC * Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) * Noise rejection function * Polarity switching Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM correction function Max 128-bytes/2 addresses Interrupts * 13 sources 8 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8-bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8-bits) 6. Timer T1H, Timer T1L 7. Vertical synchronous signal interrupt (VS), horizontal line (HS) 9. IIC, Software * Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set.
No.7936-3/17
LC863548B/40B/32B/28B/24B/20B/16B
Sub-routine stack level * A maximum of 128 levels (stack is built in the internal RAM) Multiplication/division instruction * 16-bits x 8-bits (7 instruction cycle times) * 16-bits / 8-bits (7 instruction cycle times) 3 oscillation circuits * Built-in RC oscillation circuit used for the system clock * Built-in VCO circuit used for the system clock and OSD * X'tal oscillation circuit used for base timer, system clock and PLL reference Standby function * HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. * HOLD mode The HOLD mode is used to stop the oscillations ; RC (internal), VCO, and X'tal oscillations. This mode can be released by the following conditions. 1. Pull the reset terminal (RES) to low level. 2. Feed the selected level to either P70/INT0 or P71/INT1. Package * MFP36S * DIP36S Development tools * Flash EEPROM * Evaluation chip * Emulator
: LC86F3548A : LC863096 : EVA86000 (main) + ECB863200A (evaluation chip board) + SUB863400A (sub board) + POD36-CABLE (cable) + POD36-DIP (for DIP36S) or POD36-MFP (for MFP36S)
No.7936-4/17
LC863548B/40B/32B/28B/24B/20B/16B
Package Dimensions
unit : mm 3204B
Package Dimensions
unit : mm 3170A
No.7936-5/17
LC863548B/40B/32B/28B/24B/20B/16B
Pin Assignment
P10/SDA0 P11/SCLK0 P12/SDA1 P13/SCLK1 VSS XT1 XT2 VDD P04/AN4 P05/AN5 P06/AN6 P07/AN7 RES FILT P33 P30 VS HS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
P03 P02 P01 P00 P17/PWM P16/PWM3 P15/PWM2 P14/PWM1 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P32 P31 BL B G R Top view
No.7936-6/17
LC863548B/40B/32B/28B/24B/20B/16B
System Block Diagram
Interrupt Control IR PLA
Standby Control
ROM
RC VCO
Clock Generator
X'tal
PC PLL
IIC
ROM Correct Control
ACC
XRAM
B Register
Timer 0
Bus Interface
C Register
Timer 1
Port 1 ALU
Base Timer
Port 3
ADC
Port 7
PSW
INT0 to 3 Noise Rejection Filter
RAR
PWM OSD Control Circuit CGROM VRAM
RAM
Stack Pointer
Port 0
Watch Dog Timer
No.7936-7/17
LC863548B/40B/32B/28B/24B/20B/16B
Pin Description
Pin name VSS XT1 XT2 VDD RES FILT VS HS R G B BL Port 0 P00 to P07 I/O I O I O I I O O O O I/O Negative power supply Input terminal for crystal oscillator Output terminal for crystal oscillator Positive power supply Reset terminal Filter terminal for PLL Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Fast blanking control signal Switch TV image signal and caption/OSD image signal * 8-bit input/output port Input/output can be specified in nibble unit (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) * Other functions AD converter input port (P04 to P07 : 4 channels) Port 1 P10 to P17 I/O * 8-bit input/output port Input/output can be specified for each bit (programmable pull-up resister provided) * Other functions P10 P11 P12 P13 P14 P15 P16 P17 Port 3 P30 to P33 Port 7 P70 P71 to P73 I/O I/O IIC0 data I/O IIC0 clock output IIC1 data I/O IIC1 clock output PWM1 output PWM2 output PWM3 output Timer 1 (PWM) output Output Format CMOS/Nch-OD Pull-up resistor provided/not provided Output Format CMOS/Nch-OD Function Option
* 4-bit input/output port Input/output can be specified for each bit (CMOS output/input with programmable pull-up resister) * 4-bit input/output port Input or output can be specified for each bit P70 : I/O with programmable pull-up resister P71 to P73 : CMOS output/input with programmable pull-up resister * Other function P70 P71 P72 P73 INT0 input/HOLD release input/ Nch-Tr. Output for watchdog timer INT1 input/HOLD release input INT2 input/Timer 0 event input INT3 input (noise rejection filter connected) / Timer 0 event input Interrupt receiver format, vector addresses rising INT0 INT1 INT2 INT3 enable enable enable enable falling enable enable enable enable rising/ falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable vector 03H 0BH 13H 1BH
Note : A capacitor of at least 10F must be inserted between VDD and VSS when using this IC.
Continued on next page.
No.7936-8/17
LC863548B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
* Output form and existence of pull-up resistor for all ports can be specified for each bit. * Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. * Port status in reset
Terminal Port 0 Port 1 I/O I I Pull-up resistor status at selecting CMOS output option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF
Absolute Maximum Ratings / Ta = 25C, VSS = 0V
Parameter Supply voltage Input voltage Output voltage Input/output voltage High level output current Total output current Low level output current Peak output current Total output current Maximum power dissipation Operating temperature range Storage temperature range Tstg Topr IOAH(1) IOAH(2) IOAH(3) IOPL(1) IOPL(2) IOPL(3) IOAL(1) IOAL(2) IOAL(3) Pd max Ports 0, 1 Ports 3, 7 R, G, B, BL Ports 0, 1, 3 Port 7 R, G, B, BL Ports 0, 1 Ports 3, 7 R, G, B, BL MFP36S DIP36S -10 -55 Peak output current IOPH(2) R, G, B, BL Symbol VDD max VI(1) VO(1) VIO IOPH(1) VDD RES, HS, VS R, G, B, BL, FILT Ports 0, 1, 3, 7 Ports 0, 1, 3, 7 * CMOS output * For each pin. * CMOS output * For each pin. The total of all pins. The total of all pins. The total of all pins. For each pin. For each pin. For each pin. The total of all pins. The total of all pins. The total of all pins. Ta = -10 to +70C Pins Conditions Limits VDD[V] min -0.3 -0.3 -0.3 -0.3 -4 -5 -20 -10 -12 20 15 5 40 20 12 340 500 +70 C +125 mW mA typ max +7.0 VDD+0.3 VDD+0.3 VDD+0.3 V unit
Recommended Operating Range / Ta = -10C to +70C, VSS = 0V
Parameter Operating supply voltage range Hold voltage Symbol VDD(1) VDD(2) VHD VDD VDD Pins Conditions 0.844s tCYC 0.852s 4s tCYC 400s RAMs and the registers data are kept in HOLD mode. High level input voltage VIH(1) VIH(2) Port 0 * Ports 1, 3 (Schumitt) * Port 7 (Schumitt) port input/interrupt * RES, HS, VS (Schumitt) VIH(3) Port 70 Watchdog timer input Output disable 4.5 to 5.5 VDD-0.5 VDD 4.5 to 5.5 0.75VDD VDD Output disable Output disable 4.5 to 5.5 0.6VDD VDD V 2.0 5.5 Limits VDD [V] min 4.5 4.5 typ max 5.5 5.5 unit
Continued on next page.
No.7936-9/17
LC863548B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
Parameter Low level input voltage Symbol VIL(1) VIL(2) Port 0 * Ports 1, 3 (Schumitt) * Port 7 (Schumitt) port input/interrupt * RES, HS, VS (Schumitt) VIL(3) Operation cycle time tCYC(1) tCYC(2) Oscillation frequency range FmRC Port 70 Watchdog timer input * All functions operating * OSD is not operating Internal RC oscillation Output disable 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 VSS 0.844 0.844 0.4 0.8 0.848 0.6VDD 0.852 400 3.0 s MHz 4.5 to 5.5 VSS 0.25VDD V Pins Conditions Output disable Output disable Limits VDD [V] 4.5 to 5.5 min VSS typ max 0.2VDD unit
Electrical Characteristics / Ta = -10C to +70C, VSS = 0V
Parameter High level input current Symbol IIH(1) Pins Ports 0, 1, 3, 7 Conditions * Output disable * Pull-up MOS Tr. OFF * VIN = VDD (Including the off-leak current of the output Tr.) IIH(2) Low level input current IIL(1) * RES * HS, VS Ports 0, 1, 3, 7 * Output disable * Pull-up MOS Tr. OFF * VIN = VSS (Including the off- leak current of the output Tr.) IIL(2) High level output voltage VOH(2) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) Pull-up MOS Tr. resistance Bus terminal short circuit resistance (SCL0 to SCL1, SDA0 to SDA1) Hysteresis voltage Pin capacitance CP VHIS * Ports 1, 3, 7 * RES * HS, VS All pins * f = 1MHz * Every other terminals are connected to VSS. * Ta = 25C 4.5 to 5.5 10 pF Output disable 4.5 to 5.5 0.1VDD V RBS * P10 to P12 * P11 to P13 4.5 to 5.5 130 300 Rpu VOH(1) * RES * HS, VS * CMOS output of ports 0, 1, 3, 71 to 73 R, G, B, BL Ports 0, 1, 3, 71 to 73 Ports 0, 3, 71 to 73 * R, G, B, BL * Port 1 Port 70 * Ports 0, 1, 3, 7 IOH = -0.1mA R. G. B : digital mode IOL = 10mA IOL = 1.6mA IOL = 3.0mA R. G. B : digital mode IOL = 1mA VOH = 0.9VDD 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 13 38 VDD-0.5 1.5 0.4 0.4 0.4 80 k V IOH = -1.0mA 4.5 to 5.5 VDD-1 VIN = VSS 4.5 to 5.5 -1 4.5 to 5.5 -1 * VIN = VDD 4.5 to 5.5 1 A 4.5 to 5.5 1 Limits VDD[V] min typ max unit
No.7936-10/17
LC863548B/40B/32B/28B/24B/20B/16B
IIC Input/Output Conditions / Ta = -10C to +70C, VSS = 0V
Parameter SCL Frequency BUS free time between stop to start HOLD time of start, restart condition L time of SCL H time of SCL Set-up time of restart condition HOLD time of SDA Set-up time of SDA Rising time of SDA, SCL Falling time of SDA, SCL Set-up time of stop condition Symbol fSCL tBUF tHD ; STA tLOW tHIGH tSU ; STA tHD ; DAT tSU ; DAT tR tF tSU ; STO Standard min 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 max 100 1000 300 min 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 High speed max 400 0.9 300 300 unit kHz s s s s s s ns ns ns s
Refer to figure 7 Note : Cb : Total capacitance of all BUS (unit : pF)
Pulse Input Conditions / Ta = -10C to +70C, VSS = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIH(6) tPIL(6) Pins *INT0, INT1 *INT2/T0IN INT3/T0IN (1 tCYC is selected for noise rejection clock.) INT3/T0IN (16 tCYC is selected for noise rejection clock.) INT3/T0IN (64 tCYC is selected for noise rejection clock.) RES HS, VS Reset acceptable * Display position controllable (Note) * The active edge of HS and VS must be apart at least 1 tCYC. * Refer to figure 4. Rising/falling time tTHL tTLH HS Refer to figure 4. 4.5 to 5.5 500 ns 4.5 to 5.5 3 s 4.5 to 5.5 200 * Interrupt acceptable * Timer 0-countable 4.5 to 5.5 128 * Interrupt acceptable * Timer 0-countable 4.5 to 5.5 32 tCYC Conditions * Interrupt acceptable * Timer 0-countable * Interrupt acceptable * Timer 0-countable 4.5 to 5.5 2 Limits VDD[V] 4.5 to 5.5 min 1 typ max unit
AD Converter Characteristics / Ta = -10C to +70C, VSS = 0V
Parameter Resolution Absolute precision Conversion time N ET tCAD Vref selection to conversion finish Analog input voltage range Analog port input current IAINH IAINL VAIN = VDD VAIN = VSS -1 VAIN AN4 to AN7 4.5 to 5.5 VSS VDD 1 V A (Note) 1-bit conversion time = 2 x tCYC 1.69 s Symbol Pins Conditions Limits VDD [V] min typ 6 1 max unit bit LSB
Note : Absolute precision does not include quantizing error (1/2LSB).
No.7936-11/17
LC863548B/40B/32B/28B/24B/20B/16B
Analog Mode RGB Characteristics / Ta = -10C to +70C, VSS = 0V
Parameter Analog output voltage Symbol R. G. B Analog output mode Pins Conditions Low level output Intensity output Hi level output Time setting R. G. B 70% 10pf load 5.0 Limits VDD [V] min 0.45 0.90 1.35 typ 0.5 1.0 1.5 max 0.55 1.10 1.65 50 ns V unit
Sample Current Dissipation Characteristics / Ta = -10C to +70C, VSS = 0V
The sample current dissipation characteristics are the measurement result of SANYO provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored.
Parameter Current dissipation during basic operation (Note 3) Symbol IDDOP(1) Pins VDD Conditions * FmX'tal = 32.768kHz X'tal oscillation * System clock : VCO * VCO for OSD operating * OSD is Digital mode * Internal RC oscillation stops IDDOP(2) VDD * FmX'tal = 32.768kHz X'tal oscillation * System clock : VCO * VCO for OSD operating * OSD is Analog mode * Internal RC oscillation stops IDDOP(3) VDD * FmX'tal = 32.768kHz X'tal oscillation * System clock : X'tal (Instruction cycle time : 366.2s) * VCO for system VCO for OSD, internal RC oscillation stop * Data slicer, AD converters stop Current dissipation in HALT mode (Note 3) IDDHALT(1) VDD * HALT mode * FmX'tal = 32.768kHz X'tal oscillation * System clock : VCO * VCO for OSD stops * Internal RC oscillation stops IDDHALT(2) VDD * HALT mode * FmX'tal = 32.768kHz X'tal oscillation * VCO for system stops * VCO for OSD stops * System clock : Internal RC IDDHALT(3) VDD * HALT mode * FmX'tal = 32.768kHz X'tal oscillation * VCO for system stops * VCO for OSD stops * System clock : X'tal (Instruction cycle time : 366.2s) Current dissipation in HOLD mode (Note 3) IDDHOLD VDD * HOLD mode * All oscillation stops. 4.5 to 5.5 0.05 20 A 4.5 to 5.5 35 200 A 4.5 to 5.5 300 1000 4.5 to 5.5 4 10 mA 4.5 to 5.5 50 300 A 4.5 to 5.5 21 37 mA 4.5 to 5.5 13 25 Limits VDD [V] min typ max unit
Note 3 : The currents through the output transistors and the pull-up MOS transistors are ignored.
No.7936-12/17
LC863548B/40B/32B/28B/24B/20B/16B
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions : * Recommended circuit parameters are verified by an oscillator manufacturer using a SANYO provided oscillation evaluation board. * Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70C)
Frequency 32.768kHz Manufacturer Seiko Epson Oscillator C-002RX Recommended circuit parameters C1 18pF C2 18pF Rf OPEN Rd 390k Operating supply voltage range 4.5 to 5.5V Oscillation stabilizing time typ 1.00S max 1.50S Notes
Notes : The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. * Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. * The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10C to +70C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. * When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with SANYO sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. * The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. * The capacitors' VSS should be allocated close to the microcontroller's GND terminal and be away from other GND. * The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf
Rd
C1
X'tal
C2
Figure 1 Recommended oscillation circuit
No.7936-13/17
LC863548B/40B/32B/28B/24B/20B/16B
Power supply
VDD VDD limit 0V Reset time
RES
Internal RC resonator oscillation
XT1, XT2 tmsVCO VCO for system stable
Operation mode
Unfixed
Reset
Instruction execution mode

HOLD release
Valid
Internal RC resonator oscillation
XT1, XT2 tmsVCO VCO for system stable
Operation mode
HOLD
Instruction execution mode

Figure 2 Oscillation stabilizing time
No.7936-14/17
LC863548B/40B/32B/28B/24B/20B/16B
tPIL (1) to (5)
tPIH (1) to (4)
Figure 3 Pulse input timing condition - 1
tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6)
more than 1tCYC
Figure 4 Pulse input timing condition - 2
LC863548A 10k HS HS C536
Figure 5 Recommended Interface circuit
No.7936-15/17
LC863548B/40B/32B/28B/24B/20B/16B
100 FILT + 2.2F -
1M
33000pF
Figure 6 FILT recommended circuit Note : Place FILT parts on board as close to the microcontroller as possible.
P SDA tBUF
S
Sr
P
tHD ; STA tR SCL tLOW
tF
tHD ; STA
tsp
tHD ; DAT tHIGH tSU ; DAT
tSU ; STA
tSU ; STO
S : start condition P : stop condition Sr : restart condition
tsp : Spike suppression
Standard mode : not exist High speed mode : less than 50ns
Figure 7 IIC timing
I 1mA
I
I
PAD R 500
Figure 8 R. G. B. analog output equivalent circuit
No.7936-16/17
LC863548B/40B/32B/28B/24B/20B/16B
PS No.7936-17/17

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